Power – Performance Optimization for Custom Digital Circuits

Power - Performance Optimization for Custom Digital Circuits

This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to maximize the performance of digital circuits within a limited power budget by tuning various variables such as gate sizes, supply, and threshold voltages. It can employ different models to characterize the components. Anal...

Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability

This dissertation is dedicated to my parents, Jaspal and Rajwant Dhillon, my sister, Monica and my wife, Puneet iv Acknowledgements I am grateful to my advisor, Dr. Abhijit Chatterjee, for his support and guidance throughout my graduate career. He continuously motivated me to strive for my best and this helped me to improve the quality of my dissertation. I am thankful to Dr. Adit Singh for his...

Energy-Performance Optimization of Synthesized Digital Integrated Circuits

Low-power LVDS for digital readout circuits

This paper presents a mixed-signal LVDS driver in 90 nm CMOS technology. The designed LVDS core is to be used as a data link between Infrared Focal Plane Array (IRFPA) detector end and microprocessor input. Parallel data from 220 pixels of IRFPA is serialized by LVDS driver and read out to microprocessor. It also offers a reduced power consumption rate, high data transmission speed and utilizes...

Power-Up Delay for Retiming Digital Circuits

Retiming is sometimes used to optimize gate-level sequential designs. This technique allows memory elements to be moved across combinational elements. Unfortunately, retiming may cause the environment of a design to wait for a few additional clock cycles after power-up to guarantee the same behavior as the original design. Leiserson and Saxe [1] presented a bound on this number of clock cycles;...